Computer Architecture and Organization Terminology Episode 1 ~ Ofuran

Computer Architecture and Organization Terminology Episode 1

          There are many terms which are used widely in Computer Architecture. In this post, I am going to discuss about some of those terms. As the actual and practical meaning of a term may have difference. So, all should keep in mind this terminology page in order to understand the studies of computer architecture easily.
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                          Computer Architecture and Organization  

Terms
Elaboration
PC
Personal Computer, Program Counter
I/O
Input Output
ALU
Arithmetic Logic Unit
CISC
Complex Instruction Set Computer
RISC
Reduced Instruction Set Computer
CS
Computer System
PDF
Portable Document Format
CPU
Central Processing Unit
CU
Control Unit
ENIAC
Electronic Numerical Integrator And Computer
EDVAC
Electronic Discrete Variable Computer
MBR
Memory Buffer Register
MAR
Memory Address Register
IR
Instruction Register
IBR
Instruction Buffer Register
AC
Accumulator
MQ
Multiplier Quotient
UNIVAC
Universal Automatic Computer
IC
Integrated Circuit
SSI
Small Scale Integration
OEM
Original Equipment Manufacturer
LSI
Large Scale Integration
VLSI
Very Large Scale Integration
ULSI
Ultra Large Scale Integration
RC
Resistance and Capacitance
MIC
Many Integrated Core
GPU
Graphics Processing Unit
GPGPU
General Purpose Graphics Processing Unit
ARM
Acorn RISC Machine
MIPS
Millions of Instructions Per Second
SPEC
System Performance Evaluation Corporation
JVM
Java Virtual Machine
IAC
Instruction Address Calculation
IF
Instruction Fetch
IOD
Instruction Operation Decoding
OAC
Operand Address Calculation
OF
Operand Fetch
DO
Data Operation
OS
Operand Store
ISR
Interrupt Service Routine
DMA
Direct Memory Access
LAN
Local Area Networks
WAN
Wide Area Network
SCSI
Small Computer System Interface
QPI
Quick Path Interconnect
LVDS
Low Voltage Differential Signaling
CRC
Cyclic Redundancy Check
PCI
Peripheral Component Interconnect
PCIe
PCI Express
SIG
PCI Special Interest Group
DLLPs
Data Link Layer Packets
TLPs
Transaction Layer Packets
STT
Split Transaction Technique
RAM
Random Access Memory
ROM
Read Only Memory
DRAM
Dynamic RAM
PROM
Programmable ROM
EPROM
Erasable PROM
EEPROM
Electrically Erasable PROM
SRAM
Static RAM
RAS
Row Address Select
CAS
Column Address Select
WE
Write Enable
OE
Output Enable
CLK
Clock Input
SDRAM
Synchronous DRAM
TI
Table Indicator


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